1. Field of the Invention
The present invention relates to a method of forming semiconductor device, and more particularly to a method of forming shallow trench isolation (STI).
2. Description of the Prior Art
In the integrated circuit industry today, there are in general hundreds of thousands of semiconductor devices built on a single chip. Every device on the chip must be electrically isolated to ensure that they operate independently without interfering with each other. The art of isolating semiconductor devices then becomes one important aspect of modern metaloxide-semiconductor (MOS) integrated circuit technology for the separation of different devices or different functional regions. With the semiconductor devices having high integration, improper isolation among devices will cause current leakage and then leads to significant power consumption. In addition, improper isolation may result in temporary or permanent damage of the electrical circuit.
One of the most well known techniques for isolation is local oxidation of silicon (LOCOS) which provides the isolation by oxidizing the silicon substrate to create silicon dioxide regions among active devices or functional regions. The benefits of LOCOS include simplified process and low cost because the silicon substrate is easy to be oxidized into silicon dioxide. This benefits of simplified process makes LOCOS to be the most widely used isolation technique in very large scale integrated (VLSI) circuit. However, due to the tendency for the manufacture of semiconductor integral circuit to high integration, LOCOS encounters the limitation in its scalability.
The trench isolation, or, named the shallow trench isolation (STI), is another isolation technique developed especially for semiconductor chip with high integration. Trenches are formed in the semiconductor substrate by recessing the substrate deep enough for isolation and refilling with insulating material to provide the isolation among active devices or different well regions. In general, trench isolation is more suitable for the semiconductor device having high integration in comparison with LOCOS isolation.
For deep sub-micron CMOS generation, the conventional LOCOS isolation suffers from difficulty such as large lateral extension caused by bird's beak effect, non-planarity, local field oxide thinning effect, and stress-induced silicon defects. The key challenges to LOCOS scaling are field oxide layer thinning at narrow dimension, bird's beak formation, and field-implant encroachment. For future CMOS technology, an effective device isolation method that provides abrupt transitions to active device regions with minimum impact on device characteristics or topography will be required. They come to the conclusions that STI is a more direct method of meeting these requirements.
Generally, traditional method of forming STI includes these steps of follows. A pad oxide layer is formed on a semiconductor substrate by thermal oxidation. A nitride oxide layer is formed on the pad oxide layer. A photoresistor is coated on the nitride oxide layer. A patterned photoresistor is formed, by photolithography, to define the region desired to form trenches. The nitride oxide layer and the pad oxide layer are etched to form a patterned nitride layer and a patterned pad oxide layer. Then, the region desired to form trenches is exposed. The region desired to form trenches is then anisotropically etched to form the trenches by using the patterned photoresistor as a mask. A silicon dioxide layer is formed, by CVD, on the nitride layer and then the trenches are filled with the silicon dioxide. The silicon dioxide layer is polished by CMP to achieve global planarization. Thereafter, the nitride layer is removed. Finally, the pad oxide layer is remove by diluted solution of hydrofluoric acid (DHF). Thus, fabricating process of the shallow trench isolation (STI) is accomplished.
However, the great difficulty that the above traditional method encounters is described as follows.
(a) During the CMP process, the polishing rate of the silicon dioxide layer is higher than that of the nitride oxide layer. Thus, it leads to the dishing effect. PA1 (b) During the CMP process, the ratio of the polishing selectivity of the silicon dioxide layer to the nitride oxide layer is about 3 to 5. As a result, the endpoint of the CMP process is difficult to be detected. PA1 (c) During the pad oxide layer is removed by wet etching, the removing rate of the pad oxide layer is lower than that of the silicon dioxide layer because the pad oxide layer is formed by thermal oxidation but the silicon dioxide layer is formed by CVD, respectively. Thus, the corner effect is suffered and thereby results in a higher intensity of the sub-threshold current. That is, it renders that the MOS transistors formed subsequently fail to obey the predetermined design of the electrical circuit and thereby, yield is down.